1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit device and, more particularly, to a method of manufacturing a semiconductor integrated circuit device having deep and shallow isolation grooves.
2. Description of the Prior Art
In the manufacture of a semiconductor integrated circuit device, it is sometimes necessary to form grooves having different depths, e.g., a deep isolation groove for isolating elements from each other and a shallow isolation groove for isolating regions in each element. For example, in a bipolar semiconductor integrated circuit device, it is required to form a shallow groove for isolating a collector and a base from each other at the upper portion of a buried collector layer and a deep isolation groove which extends through the buried collector layer to isolate elements from each other.
FIGS. 1A to 1C are sectional views showing steps in the manufacture of isolation grooves of this type, which is disclosed in Japanese Patent Laid-Open No. 57-204144.
As shown in FIG. 1A, a buried collector layer 2 is formed on a p-type silicon substrate 1, and an n-type epitaxial layer 3 is epitaxially grown on the buried collector layer 2. The surface is then thermally oxidized to form a silicon oxide film 4, and a silicon nitride film 5 is formed on the silicon oxide film 4 using the CVD method.
As shown in FIG. 1B, the silicon nitride film 5 in a collector isolation region 8a and an element isolation region 9a is removed by the photoetching method. The silicon oxide film 4 exposed to the element isolation region 9a is removed by photoetching. Subsequently, the silicon is etched by reactive sputter etching to form a groove having a predetermined depth in the element isolation region 9a.
As shown in FIG. 1C, the silicon oxide film 4 on the collector isolation region 8a is etched and removed using an HF solution. The silicon is etched again using the reactives putter etching method, thereby completing a shallow collector isolation groove 8 reaching the buried collector layer 2, and a deep element isolation groove 9 extending through the buried collector layer 2.
This method is characterized in that, first of all, a groove is formed to a depth corresponding to the difference in depth between the shallow and deep grooves, and the two grooves are then simultaneously formed. According to this method, the two grooves each having an accurate depth can be formed.
FIGS. 2A to 2C are sectional views showing steps in the manufacture of grooves of this type, according to another method proposed in Japanese Patent Laid-Open No. 4-20261.
As shown in FIG. 2A, as in the first conventional method, a buried collector layer 2 is formed on a p-type silicon substrate 1, and an n-type epitaxial layer 3 is formed on the buried collector layer 2. Thereafter, the surface is thermally oxidized to form a silicon oxide film 4, and a silicon nitride film 5 is formed thereon. In this method, a PSG film 12 is formed on the resultant structure using the CVD method.
As shown in FIG. 2B, the PSG film 12, the silicon nitride film 5, and the silicon oxide film 4 in an element isolation region 9a are etched and removed by photoetching to expose the surface of the silicon substrate. Subsequently, the PSG film 12 in a collector isolation region 8a is etched and removed to expose the surface of the silicon nitride film 5.
The entire surface is simultaneously etched using the reactive ion etching method. At this time, the silicon nitride film 5 and the silicon oxide film 4 are etched in the collector isolation region 8a, and the silicon is etched in the element isolation region 9a. The surface of the silicon substrate is exposed in the collector isolation region 8a while a groove having a predetermined depth is formed in the element isolation region. The silicon substrate is further etched from this state, thereby completing a collector isolation groove 8 and an element isolation groove 9 (FIG. 2C).
According to the above-described first conventional manufacturing method, after the silicon nitride film in the collector isolation region 8a and the element isolation region 9a is removed, the oxide film in the element isolation region 9a is removed. In this case, in consideration of the patterning accuracy or misalignment of the two patterns, a first-time silicon oxide film etching pattern 14 (indicated by broken lines) for forming the deep groove is formed wider than a silicon nitride film etching pattern 13 indicated by solid lines, as shown in FIG. 3. For this reason, at the connecting portions between the collector isolation region 8a and the element isolation region 9a, which are indicated by symbol A, the silicon oxide film 4 in the collector isolation region 8a is removed together with the oxide film in the element isolation region 9a. As a result, a deep groove is formed in the collector isolation region, and the collector region is decreased to cause an increase in collector resistance or degradation in element characteristics. As the semiconductor integrated circuit becomes finer, this problem becomes more serious.
In addition, according to this conventional method, the silicon nitride film is used as an etching mask when the silicon is etched. However, the etching rate of the silicon is not so different from that of the silicon nitride film. Therefore, the thickness of the silicon nitride film must be increased, and a stress is applied in the semiconductor substrate.
According to the above-described second conventional manufacturing method, the difference in depth between the collector isolation groove 8 and the element isolation groove 9 depends on the thickness of the silicon nitride film. Therefore, it is difficult to form a groove having an accurate depth. The thickness of the silicon nitride film tends to vary due to a difference in thickness at the time of film formation, or a difference in etching depth in the etching and removing process of the PSG film on the collector isolation region 8a. Accordingly, the difference in depth between the collector isolation groove and the element isolation groove largely varies.
With the recent advance in micropatterning of semiconductor integrated circuit devices, a collector buried layer or n-type epitaxial layer gradually becomes thinner. This tendency is remarkably observed in SOI (Silicon on Insulator) integrated circuits. Accordingly, it is required to exactly control the depth of an isolation groove. However, the above-described second conventional method can hardly cope with this tendency.